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74ACT715*74ACT715-R Programmable Video Sync Generator
November 1988 Revised December 1998
74ACT715*74ACT715-R Programmable Video Sync Generator
General Description
The ACT715 and ACT715-R are 20-pin TTL-input compatible devices capable of generating Horizontal, Vertical and Composite Sync and Blank signals for televisions and monitors. All pulse widths are completely definable by the user. The devices are capable of generating signals for both interlaced and noninterlaced modes of operation. Equalization and serration pulses can be introduced into the Composite Sync signal when needed. Four additional signals can also be made available when Composite Sync or Blank are used. These signals can be used to generate horizontal or vertical gating pulses, cursor position or vertical Interrupt signal. These devices make no assumptions concerning the system architecture. Line rate and field/frame rate are all a function of the values programmed into the data registers, the status register, and the input clock frequency. The ACT715 is mask programmed to default to a Clock Disable state. Bit 10 of the Status Register, Register 0, defaults to a logic "0". This facilitates (re)programming before operation. The ACT715-R is the same as the ACT715 in all respects except that the ACT715-R is mask programmed to default to a Clock Enabled state. Bit 10 of the Status Register defaults to a logic "1". Although completely (re)programmable, the ACT715-R version is better suited for applications using the default 14.31818 MHz RS-170 register values. This feature allows power-up directly into operation, following a single CLEAR pulse.
Features
s Maximum Input Clock Frequency > 130 MHz s Interlaced and non-interlaced formats available s Separate or composite horizontal and vertical Sync and Blank signals available s Complete control of pulse width via register programming s All inputs are TTL compatible s 8 mA drive on all outputs s Default RS170/NTSC values mask programmed into registers s ACT715-R is mask programmed to default to a Clock Enable state for easier start-up into 14.31818 MHz RS170 timing
Ordering Code:
Order Number 74ACT715SC 74ACT715PC 74ACT715-RSC 74ACT715-RPC Package Number M20B N20A M20B N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignment for DIP and SOIC
FACTTM is a trademark of Fairchild Semiconductor Corporation.
(c) 1999 Fairchild Semiconductor Corporation
DS010137.prf
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74ACT715*74ACT715-R
Logic Block Diagram
Pin Description
There are a Total of 13 inputs and 5 outputs on the ACT715. Data Inputs D0-D7: The Data Input pins connect to the Address Register and the Data Input Register. ADDR/DATA: The ADDR/DATA signal is latched into the device on the falling edge of the LOAD signal. The signal determines if an address (0) or data (1) is present on the data bus. L/HBYTE: The L/HBYTE signal is latched into the device on the falling edge of the LOAD signal. The signal determines if data will be read into the 8 LSB's (0) or the 4 MSB's (1) of the Data Registers. A 1 on this pin when an ADDR/DATA is a 0 enables Auto-Load Mode. LOAD: The LOAD control pin loads data into the Address or Data Registers on the rising edge. ADDR/DATA and L/ HBYTE data is loaded into the device on the falling edge of the LOAD. The LOAD pin has been implemented as a Schmitt trigger input for better noise immunity. CLOCK: System CLOCK input from which all timing is derived. The clock pin has been implemented as a Schmitt trigger for better noise immunity. The CLOCK and the LOAD signal are asynchronous and independent. Output state changes occur on the falling edge of CLOCK. CLR: The CLEAR pin is an asynchronous input that initializes the device when it is HIGH. Initialization consists of setting all registers to their mask programmed values, and initializing all counters, comparators and registers. The CLEAR pin has been implemented as a Schmitt trigger for better noise immunity. A CLEAR pulse should be asserted by the user immediately after power-up to ensure proper initialization of the registers--even if the user plans to (re)program the device.
Note: A CLEAR pulse will disable the CLOCK on the ACT715 and will enable the CLOCK on the ACT715-R.
ODD/EVEN: Output that identifies if display is in odd (HIGH) or even (LOW) field of interlace when device is in interlaced mode of operation. In noninterlaced mode of operation this output is always HIGH. Data can be serially scanned out on this pin during Scan Mode. VCSYNC: Outputs Vertical or Composite Sync signal based on value of the Status Register. Equalization and Serration pulses will (if enabled) be output on the VCSYNC signal in composite mode only. VCBLANK: Outputs Vertical or Composite Blanking signal based on value of the Status Register. HBLHDR: Outputs Horizontal Blanking signal, Horizontal Gating signal or Cursor Position based on value of the Status Register. HSYNVDR: Outputs Horizontal Sync signal, Vertical Gating signal or Vertical Interrupt signal based on value of Status Register.
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74ACT715*74ACT715-R
Register Description
All of the data registers are 12 bits wide. Width's of all pulses are defined by specifying the start count and end count of all pulses. Horizontal pulses are specified withrespect-to the number of clock pulses per line and vertical pulses are specified with-respect-to the number of lines per frame. REG0--STATUS REGISTER The Status Register controls the mode of operation, the signals that are output and the polarity of these outputs. The default value for the Status Register is 0 (000 Hex) for the ACT715 and is "1024" (400 Hex) for the ACT715-R. Bits 0-2 B2 B1 B0 VCBLANK VCSYNC HBLHDR HSYNVDR 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CBLANK VBLANK CBLANK VBLANK CBLANK VBLANK CBLANK VBLANK CSYNC CSYNC VSYNC VSYNC CSYNC CSYNC VSYNC VSYNC Bits 3-4 B4 0 B3 0 Equalization (DEFAULT) 0 1 1 1 0 1 Non Interlaced Double Serration Illegal State Mode of Operation Interlaced Double Serration and HGATE HBLANK HGATE HBLANK CUSOR HBLANK CUSOR HBLANK VGATE VGATE HSYNC HSYNC VINT VINT HSYNC HSYNC (DEFAULT)
B10--
Disable System Clock (0) Enable System Clock (1) Default values for B10 are "0" in the ACT715 and "1" in the ACT715-R.
B11--
Disable Counter Test Mode (0) Enable Counter Test Mode (1) This bit is not intended for the user but is for internal testing only.
HORIZONTAL INTERVAL REGISTERS The Horizontal Interval Registers determine the number of clock cycles per line and the characteristics of the Horizontal Sync and Blank pulses. REG1-- REG2-- REG3-- REG4-- Horizontal Front Porch Horizontal Sync Pulse End Time Horizontal Blanking Width Horizontal Interval Width # of Clocks per Line
VERTICAL INTERVAL REGISTERS The Vertical Interval Registers determine the number of lines per frame, and the characteristics of the Vertical Blank and Sync Pulses. REG5-- REG6-- REG7-- REG8-- Vertical Front Porch Vertical Sync Pulse End Time Vertical Blanking Width Vertical Interval Width per Frame # of Lines
EQUALIZATION AND SERRATION PULSE SPECIFICATION REGISTERS These registers determine the width of equalization and serration pulses and the vertical interval over which they occur.
REG 9-- Equalization Pulse Width End Time Non Interlaced Single Serration and Equalization REG10-- Serration Pulse Width End Time Double Equalization and Serration mode will output equalREG11-- Equalization/Serration Pulse Vertical ization and serration pulses at twice the HSYNC frequency Interval Start Time (i.e., 2 equalization or serration pulses for every HSYNC REG12-- Equalization/Serration Pulse Vertical pulse). Single Equalization and Serration mode will output Interval End Time an equalization or serration pulse for every HSYNC pulse. In Interlaced mode equalization and serration pulses will be VERTICAL INTERRUPT SPECIFICATION REGISTERS output during the VBLANK period of every odd and even These Registers determine the width of the Vertical Interfield. Interlaced Single Equalization and Serration mode is rupt signal if used. not possible with this part. REG13-- Bits 5-8 Bits 5 through 8 control the polarity of the outputs. A value of zero in these bit locations indicates an output pulse active LOW. A value of 1 indicates an active HIGH pulse. B5-- B6-- B7-- B8-- Bits 9-11 Bits 9 through 11 enable several different features of the device. B9-- Enable Equalization/Serration Pulses (0) Disable Equalization/Serration Pulses (1) VCBLANK Polarity VCSYNC Polarity HBLHDR Polarity HSYNVDR Polarity REG14-- Vertical Interrupt Activate Time Vertical Interrupt Deactivate Time
CURSOR LOCATION REGISTERS These 4 registers determine the cursor position location, or they generate separate Horizontal and Vertical Gating signals. REG15-- REG16-- REG17-- REG18-- Horizontal Cursor Position Start Time Horizontal Cursor Position End Time Vertical Cursor Position Start Time Vertical Cursor Position End Time
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74ACT715*74ACT715-R
Signal Specification
HORIZONTAL SYNC AND BLANK SPECIFICATIONS All horizontal signals are defined by a start and end time. The start and end times are specified in number of clock cycles per line. The start of the horizontal line is considered pulse 1 not 0. All values of the horizontal timing registers are referenced to the falling edge of the Horizontal Blank signal (see Figure 1). Since the first CLOCK edge, CLOCK #1, causes the first falling edge of the Horizontal Blank ref-
erence pulse, edges referenced to this first Horizontal edge are n + 1 CLOCKs away, where "n" is the width of the timing in question. Registers 1, 2, and 3 are programmed in this manner. The horizontal counters start at 1 and count until HMAX. The value of HMAX must be divisible by 2. This limitation is imposed because during interlace operation this value is internally divided by 2 in order to generate serration and equalization pulses at 2 x the horizontal frequency. Horizontal signals will change on the falling edge of the CLOCK signal. Signal specifications are shown below.
FIGURE 1. Horizontal Waveform Specification Horizontal Period (HPER) Horizontal Blanking Width: Horizontal Sync Width: Horizontal Front Porch: = REG(4) x ckper = [REG(3) - 1] x ckper Vertical Syncing Width = [REG(6) - REG(5)] x hper/n Vertical Front Porch = [REG(5) - 1] x hper/n where n = 1 for noninterlaced n = 2 for interlaced COMPOSITE SYNC AND BLANK SPECIFICATION Composite Sync and Blank signals are created by logically ANDing (ORing) the active LOW (HIGH) signals of the corresponding vertical and horizontal components of these signals. The Composite Sync signal may also include serration and/or equalization pulses. The Serration pulse interval occurs in place of the Vertical Sync interval. Equalization pulses occur preceding and/or following the Serration pulses. The width and location of these pulses can be programmed through the registers shown below. (See Figure 3.) Horizontal Equalization PW = [REG(9) - REG(1)] x ckper REG 9 = (HFP) + (HEQP) + 1 Horizontal Serration PW: = [REG(4)/n REG(10)] x ckper Where + REG(1) -
= [REG(2) - REG(1)] x ckper = [REG(1) - 1] x ckper
VERTICAL SYNC AND BLANK SPECIFICATION All vertical signals are defined in terms of number of lines per frame. This is true in both interlaced and noninterlaced modes of operation. Care must be taken to not specify the Vertical Registers in terms of lines per field. Since the first CLOCK edge, CLOCK #1, causes the first falling edge of the Vertical Blank (first Horizontal Blank) reference pulse, edges referenced to this first edge are n + 1 lines away, where "n" is the width of the timing in question. Registers 5, 6, and 7 are programmed in this manner. Also, in the interlaced mode, vertical timing is based on half-lines. Therefore registers 5, 6, and 7 must contain a value twice the total horizontal (odd and even) plus 1 (as described above). In non-interlaced mode, all vertical timing is based on whole-lines. Register 8 is always based on whole-lines and does not add 1 for the first clock. The vertical counter starts at the value of 1 and counts until the value of VMAX. No restrictions exist on the values placed in the vertical registers. Vertical Blank will change on the leading edge of HBLANK. Vertical Sync will change on the leading edge of HSYNC. (See Figure 2.) Vertical Frame Period (VPER) = REG(8) x hper Vertical Field Period (VPER/n) = REG(8) x hper/n Vertical Blanking Width = [REG(7) - 1] x hper/n www.fairchildsemi.com 4
REG 10 = (HFP) + (HPER/2) - (HSERR) + 1 n = 1 for noninterlaced single serration/equalization n = 2 for noninterlaced double serration/equalization n = 2 for interlaced operation
74ACT715*74ACT715-R
FIGURE 2. Vertical Waveform Specification
FIGURE 3. Equalization/Serration Interval Programming HORIZONTAL AND VERTICAL GATING SIGNALS Horizontal Drive and Vertical Drive outputs can be utilized as general purpose Gating Signals. Horizontal and Vertical Gating Signals are available for use when Composite Sync and Blank signals are selected and the value of Bit 2 of the Status Register is 0. The Vertical Gating signal will change in the same manner as that specified for the Vertical Blank. Horizontal Gating Signal Width = [REG(16) - REG(15)] x ckper Vertical Gating Signal Width: hper = [REG(18) - REG(17)] x CURSOR POSITION AND VERTICAL INTERRUPT The Cursor Position and Vertical Interrupt signal are available when Composite Sync and Blank signals are selected and Bit 2 of the Status Register is set to the value of 1. The Cursor Position generates a single pulse of n clocks wide during every line that the cursor is specified. The signals are generated by logically ORing (ANDing) the active LOW (HIGH) signals specified by the registers used for generating Horizontal and Vertical Gating signals. The Vertical Interrupt signal generates a pulse during the vertical interval specified. The Vertical Interrupt signal will change in the same manner as that specified for the Vertical Blanking signal. Horizontal Cursor Width = [REG(16) - REG(15)] x ckper Vertical Cursor Width = [REG(18) - REG(17)] x hper Vertical Interrupt Width = [REG(14) - REG(13)] x hper
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74ACT715*74ACT715-R
Addressing Logic
The register addressing logic is composed of two blocks of logic. The first is the address register and counter (ADDRCNTR), and the second is the address decode (ADDRDEC). ADDRCNTR LOGIC Addresses for the data registers can be generated by one of two methods. Manual addressing requires that each byte of each register that needs to be loaded needs to be addressed. To load both bytes of all 19 registers would require a total of 57 load cycles (19 address and 38 data cycles). Auto Addressing requires that only the initial register value be specified. The Auto Load sequence would require only 39 load cycles to completely program all registers (1 address and 38 data cycles). In the auto load sequence the low order byte of the data register will be
written first followed by the high order byte on the next load cycle. At the time the High Byte is written the address counter is incremented by 1. The counter has been implemented to loop on the initial value loaded into the address register. For example: If a value of 0 was written into the address register then the counter would count from 0 to 18 before resetting back to 0. If a value of 15 was written into the address register then the counter would count from 15 to 18 before looping back to 15. If a value greater than or equal to 18 is placed into the address register the counter will continuously loop on this value. Auto addressing is initiated on the falling edge of LOAD when ADDRDATA is 0 and LHBYTE is 1. Incrementing and loading of data registers will not commence until the falling edge of LOAD after ADDRDATA goes to 1. The next rising edge of LOAD will load the first byte of data. Auto Incrementing is disabled on the falling edge of LOAD after ADDRDATA and LHBYTE goes low.
Manual Addressing Mode
Cycle # 1 2 3 4 5 6 Load Falling Edge Enable Manual Addressing Enable Lbyte Data Load Enable Hbyte Data Load Enable Manual Addressing Enable Lbyte Data Load Enable Hbyte Data Load Load Rising Edge Load Address m Load Lbyte m Load Hbyte m Load Address n Load Lbyte n Load Hbyte n
Auto Addressing Mode
Cycle # 1 2 3 4 5 6 Load Falling Edge Enable Auto Addressing Enable Lbyte Data Load Enable Hbyte Data Load Enable Lbyte Data Load Enable Hbyte Data Load Enable Manual Addressing Load Rising Edge Load Start Address n Load Lbyte (n) Load Hbyte (n); Inc Counter Load Lbyte (n+1) Load Hbyte (n+1); Inc Counter Load Address
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74ACT715*74ACT715-R
ADDRDEC LOGIC The ADDRDEC logic decodes the current address and generates the enable signal for the appropriate register. The enable values for the registers and counters change on the falling edge of LOAD. Two types of ADDRDEC logic is enabled by 2 pair of addresses, Addresses 22 or 54 (Vectored Restart logic) and Addresses 23 or 55 (Vectored Clear logic). Loading these addresses will enable the appropriate logic and put the part into either a Restart (all counter registers are reinitialized with preprogrammed data) or Clear (all registers are cleared to zero) state. Reloading the same ADDRDEC address will not cause any change in the state of the part. The outputs during these states are frozen and the internal CLOCK is disabled. Clocking the part during a Vectored Restart or Vectored Clear state will have no effect on the part. To resume operation in the new state, or disable the Vectored Restart or Vectored Clear state, another non-ADDRDEC address must be loaded. Operation will begin in the new state on the rising edge of the non-ADDRDEC load pulse. It is recommended that an unused address be loaded following an ADDRDEC operation to prevent data registers from accidentally being corrupted. The following Addresses are used by the device. Address 0 Status Register REG0 Address 1-18Data Registers REG1-REG18 Address 19-21Unused Address 22/54Restart Vector (Restarts Device) Address 23/55Clear Vector (Zeros All Registers) Address 24-31Unused Address 32-50Register Scan Addresses Address 51-53Counter Scan Addresses Address 56-63Unused At any given time only one register at most is selected. It is possible to have no registers selected. VECTORED RESTART ADDRESS The function of addresses 22 (16H) or 54 (36H) are similar to that of the CLR pin except that the preprogramming of the registers is not affected. It is recommended but not required that this address is read after the initial device configuration load sequence. A 1 on the ADDRDATA pin (Auto Addressing Mode) will not cause this address to automatically increment. The address will loop back onto itself regardless of the state of ADDRDATA unless the address on the Data inputs has been changed with ADDRDATA at 0. VECTORED CLEAR ADDRESS Addresses 23 (17H) or 55 (37H) is used to clear all registers to zero simultaneously. This function may be desirable to use prior to loading new data into the Data or Status Registers. This address is read into the device in a similar fashion as all of the other registers. A 1 on the ADDRDATA pin (Auto Addressing Mode) will not cause this address to automatically increment. The address will loop back onto itself regardless of the state of ADDRDATA unless the address on the Data inputs has been changed with ADDRDATA at 0.
FIGURE 4. ADDRDEC Timing GEN LOCKING The ACT715 and ACT715-R is designed for master SYNC and BLANK signal generation. However, the devices can be synchronized (slaved) to an external timing signal in a limited sense. Using Vectored Restart, the user can reset the counting sequence to a given location, the beginning, at a given time, the rising edge of the LOAD that removes Vector Restart. At this time the next CLOCK pulse will be CLOCK 1 and the count will restart at the beginning of the first odd line. Preconditioning the part during normal operation, before the desired synchronizing pulse, is necessary. However, since LOAD and CLOCK are asynchronous and independent, this is possible without interruption or data and performance corruption. If the defaulted 14.31818 MHz RS-170 values are being used, preconditioning and restarting can be minimized by using the CLEAR pulse instead of the Vectored Restart operation. The ACT715-R is better suited for this application because it eliminates the need to program a 1 into Bit 10 of the Status Register to enable the CLOCK. Gen Locking to another count location other than the very beginning or separate horizontal/vertical resetting is not possible with the ACT715 nor the ACT715-R. SCAN MODE LOGIC A scan mode is available in the ACT715 that allows the user to non-destructively verify the contents of the registers. Scan mode is invoked through reading a scan address into the address register. The scan address of a given register is defined by the Data register address + 32. The internal Clocking signal is disabled when a scan address is read. Disabling the clock freezes the device in it's present state. Data can then be serially scanned out of the data registers through the ODD/EVEN Pin. The LSB will be scanned out first. Since each register is 12 bits wide, completely scanning out data of the addressed register will require 12 CLOCK pulses. More than 12 CLOCK pulses on the same register will only cause the MSB to repeat on the output. Re-scanning the same register will require that register to be reloaded. The value of the two horizontal counters and 1 vertical counter can also be scanned out by using address numbers 51-53. Note that before the part will scan out the data, the LOAD signal must be brought back HIGH. Normal device operation can be resumed by loading in a non-scan address. As the scanning of the registers is a non-destructive scan, the device will resume correct operation from the point at which it was halted.
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74ACT715*74ACT715-R
RS170 Default Register Values
The tables below show the values programmed for the RS170 Format (using a 14.31818 MHz clock signal) and how they compare against the actual EIA RS170 Specifications. The default signals that will be output are CSYNC, CBLANK, HDRIVE and VDRIVE. The device initially starts Reg REG0 REG0 REG1 REG2 REG3 REG4 REG5 REG6 REG7 REG8 REG9 REG10 REG11 REG12 REG13 REG14 REG15 REG16 REG17 REG18 D Value H 0 1024 23 91 157 910 7 13 41 525 57 410 1 19 41 526 911 92 1 21
at the beginning of the odd field of interlace. All signals have active low pulses and the clock is disabled at power up. Registers 13 and 14 are not involved in the actual signal information. If the Vertical Interrupt was selected so that a pulse indicating the active lines would be output.
Register Description
000 Status Register (715) 400 Status Register (715-R) 017 HFP End Time 05B HSYNC Pulse End Time 09D HBLANK Pulse End Time 38E Total Horizontal Clocks 007 VFP End Time 00D VSYNC Pulse End Time 029 VBLANK Pulse End Time 20D Total Vertical Lines 039 Equalization Pulse End Time 19A Serration Pulse Start Time 001 Pulse Interval Start Time 013 Pulse Interval End Time 029 Vertical Interrupt Activate Time 20E Vertical Interrupt Deactivate Time 38F Horizontal Drive Start Time 05C Horizontal Drive End Time 001 Vertical Drive Start Time 015 Vertical Drive End Time Rate Period 69.841 ns 63.556 s 16.683 ms 33.367 ms
Input Clock Line Rate Field Rate Frame Rate
14.31818 MHz 15.73426 kHz 59.94 Hz 29.97 Hz
RS170 Horizontal Data
Signal HFP HSYNC Width HBLANK Width HDRIVE Width HEQP Width HSERR Width HPER iod Width 22 Clocks 68 Clocks 156 Clocks 91 Clocks 34 Clocks 68 Clocks 910 Clocks s 1.536 4.749 10.895 6.356 2.375 4.749 63.556 7.47 17.15 10.00 3.74 7.47 100 %H Specification (s) 1.5 0.1 4.7 0.1 10.9 0.2 0.1H 0.005H 2.3 0.1 4.7 0.1
RS170 Vertical Data
VFP VSYNC Width VBLANK Width VDRIVE Width VEQP Intrvl VPERiod (field) VPERiod (frame) 3 Lines 3 Lines 20 Lines 11.0 Lines 9 Lines 262.5 Lines 525 Lines 16.683 ms 33.367 ms 190.67 190.67 1271.12 699.12 7.62 4.20 3.63 6 EQP Pulses 6 Serration Pulses 0.075V 0.005V 0.04V 0.006V 9 Lines/Field 16.683 ms/Field 33.367 ms/Frame
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74ACT715*74ACT715-R
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC +0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source or Sink Current (I O ) DC VCC or Ground Current per Output Pin (I CC or IGND) Storage Temperature (TSTG) 20 mA -65C to +150C 15 mA -20 mA +20 mA -0.5V to V CC +0.5V -20 mA +20 mA -0.5V to V CC +0.5V -0.5V to +7.0V
Junction Temperature (TJ) PDIP 140C
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of FACTTM circuits outside databook specifications.
4.5V to 5.5V 0V to VCC 0V to VCC -40C to +85C
DC Electrical Characteristics
For ACT Family Devices over Operating Temperature Range (unless otherwise specified) TA = +25C Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IOLD IOHD IIN ICC ICCT Minimum Dynamic Output Current Minimum Dynamic Output Current Maximum Input Leakage Current Supply Current Quiescent Maximum ICC/Input 5.5 0.6 1.5 mA VIN = VCC - 2.1V
Note 2: All outputs loaded; thresholds on input associated with input under test. Note 3: Test Load 50 pF, 500 to Ground.
CL = 50 pF Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.001 0.001 0.1 0.1 0.36 0.36
TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 32.0 -32.0
Units V V V V V V V V V V mA mA A A
Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VIL/VIH IOH = -8 mA (Note 2) IOUT = 50 A VIN = VIL/VIH IOH = +8 mA (Note 2) VOLD = 1.65V VOHD = 3.85V VI = VCC, GND VIN = VCC, GND
5.5 5.5 5.5 5.5 0.1 8.0
1.0 80
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74ACT715*74ACT715-R
AC Electrical Characteristics
TA = +25C Symbol fMAXI fmax tPLH1 tPHL1 tPLH2 tPHL2 tPLH3 Clock to ODDEVEN (Scan Mode) Load to Outputs 5.0 4.0 11.5 16.0 3.0 19.5 ns 5.0 4.5 15.0 17.0 3.5 20.5 ns Parameter Interlaced fmax (HMAX/2 is ODD) Non-Interlaced fmax (HMAX/2 is EVEN) Clock to Any Output 5.0 4.0 13.0 15.5 3.5 18.5 ns 5.0 190 220 175 MHz VCC (V) 5.0 Min 170 CL = 50 pF Typ 190 Max TA = -40C to +85C CL = 50 pF Min 150 Max MHz Units
AC Operating Requirements
Symbol Parameter Control Setup Time tsc tsc tsd thc ADDR/DATA to LOAD- L/HBYTE to LOAD- Data Setup Time D7-D0 to LOAD+ Control Hold Time LOAD- to ADDR/DATA LOAD- to L/HBYTE Data Hold Time thd trec twld- twld+ twclr twck LOAD+ to D7-D0 LOAD+ to CLK (Note 4) Load Pulse Width LOW HIGH CLR Pulse Width HIGH CLOCK Pulse Width (HIGH or LOW)
Note 4: Removal of Vectored Reset or Restart to Clock.
VCC (V) 5.0
TA = +25C Typ 3.0 3.0
TA = -40C to +85C Guaranteed Minimums 4.0 4.0 4.0 1.0 1.0 2.0 7.0 5.5 5.0 6.5 3.0 4.5 4.5 4.5 1.0 1.0 2.0 8.0 5.5 7.5 9.5 3.5
Units
ns ns ns ns ns ns ns ns ns ns ns
5.0 5.0
2.0 0 0
5.0 5.0 5.0 5.0 5.0 5.0
1.0 5.5 3.0 3.0 5.5 2.5
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 7.0 17.0 Units pF pF V CC = 5.0V V CC = 5.0V Conditions
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74ACT715*74ACT715-R
Capacitance
(Continued)
FIGURE 5. AC Specifications
Additional Applications Information
POWERING UP The ACT715 default value for Bit 10 of the Status Register is 0. This means that when the CLEAR pulse is applied and the registers are initialized by loading the default values the CLOCK is disabled. Before operation can begin, Bit 10 must be changed to a 1 to enable CLOCK. If the default values are needed (no other programming is required) then Figure 6 illustrates a hardwired solution to facilitate the enabling of the CLOCK after power-up. Should control signals be difficult to obtain, Figure 7 illustrates a possible solution to automatically enable the CLOCK upon powerup. Use of the ACT715-R eliminates the need for most of this circuitry. Modifications of the Figure 7 circuit can be made to obtain the lone CLEAR pulse still needed upon power-up. Note that, although during a Vectored Restart none of the preprogrammed registers are affected, some signals are affected for the duration of one frame only. These signals are the Horizontal and Vertical Drive signals. After a Vectored Restart the beginning of these signals will occur at the first CLK. The end of the signals will occur as programmed. At the completion of the first frame, the signals will resume to their programmed start and end time. PREPROGRAMMING "ON-THE-FLY" Although the ACT715 and ACT715-R are completely programmable, certain limitations must be set as to when and how the parts can be reprogrammed. Care must be taken when reprogramming any End Time registers to a new value that is lower than the current value. Should the reprogramming occur when the counters are at a count after the new value but before the old value, then the counters will continue to count up to 4096 before rolling over. For this reason one of the following two precautions are recommended when reprogramming "on-the-fly". The first recommendation is to reprogram horizontal values during the horizontal blank interval only and/or vertical values during the vertical blank interval only. Since this would require delicate timing requirements the second recommendation may be more appropriate. The second recommendation is to program a Vectored Restart as the final step of reprogramming. This will ensure that all registers are set to the newly programmed values and that all counters restart at the first CLK position. This will avoid overrunning the counter end times and will maintain the video integrity.
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74ACT715*74ACT715-R
FIGURE 6. Default RS170 Hardwire Configuration
Note: A 74HC221A may be substituted for the 74HC423A Pin 6 and Pin 14 must be hardwired to GND Components R1: 4.7k R2:10k C1: 10 F C2: 50 pF
FIGURE 7. Circuit for Clear and Load Pulse Generation
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74ACT715*74ACT715-R
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body Package Number M20B
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74ACT715*74ACT715-R Programmable Video Sync Generator
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body Package Number N20A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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